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TDA7435
DIGITALLY CONTROLLED AUDIO PROCESSOR WITH LOUDSPEAKERS EQUALIZER
INPUT - FOUR HIGH PASS CHANNELS - TWO AUX STEREO CHANNELS VOLUME CONTROL IN 1dB STEPS WITH GAIN UP TO 15dB SOFT MUTE AND DIRECT MUTE FOUR AUXILIARY CHANNELS: - TWO SPEAKERS CONTROL IN 1dB STEP - TWO CHANNELS MULTIPLEXED WITH THE HIGH PASS CHANNELS ALL FUNCTIONS PROGRAMMABLE VIA SERIAL I2 CBUS DESCRIPTION The audioprocessor TDA7435 is an upgrade of the TDA731X audioprocessor family. Due to a highly linear signal processing, using CMOS-switching techniques instead of standard bipolar multipliers, very low distortion and very low noise are obtained. BLOCK DIAGRAM
CSM 22 21 20 19 18 17 16 15 6 7 MUX HP FILTER HP FILTER HP FILTER SOFT MUTE HP FILTER 3 SDA SCL DGND AGND CREF 27
2
SO28 ORDERING NUMBER: TDA7435D
A second programmable high pass filtering provides the loudspeakers equalization. The soft Mute function is implemented andcan be activated in two ways: 1 Via serial bus (Mute byte, bit D0) 2 Directly on pin 3 through an I/O line of the microcontroller Very low DC stepping is obtained by use of a BICMOS technology.
VCC 28 12
26
25
24
23
HP FL 1 HP FL 2 HP FR 1 HP FR 2 HP RL 1 HP RL 2 HP RR 1 HP RR 2 AUX 2 IN L AUX 2 IN R
I C BUS
SUPPLY
OUT REF
10 11 13 14 9 8 5
HP FL OUT HP FR OUT HP RL OUT HP RR OUT AUX 2 OUT L AUX 2 OUT R AUX 1 OUT L
1 AUX 1 IN L AUX 1 IN R 2 GAIN 0-15dB/1dB step
ATTENUATOR 0/-79dB ATTENUATOR 0/-79dB
4
AUX 1 OUT R
D96AU437A
November 1996
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ABSOLUTE MAXIMUM RATINGS
Symbol VS Tamb Tstg Operating Supply Voltage Operating Ambient Temperature Storage Temperature Range Parameter Value 10.5 -40 to 85 -55 to 150 Unit V C C
PIN CONNECTION
AUX 1 IN L AUX 1 IN R CSM AUX 1 OUT R AUX 1 OUT L AUX 2 IN L AUX 2 IN R AUX 2 OUT R AUX 2 OUT L HP FL OUT HP FR OUT OUT REF HP RL OUT HP RR OUT
1 2 3 4 5 6 7 8 9 10 11 12 13 14
D96AU438
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VCC SDA SCL DGND AGND CREF HP FL 1 HP FL 2 HP FR 1 HP FR 2 HP RL 1 HP RL 2 HP RR 1 HP RR 2
THERMAL DATA
Symbol Rth j-amb Parameter Thermal Resistance Junction-pins Value 65 Unit C/W
QUICK REFERENCE DATA
Symbol VS VCL THD S/N SC Supply Voltage Max. input signal handling Total Harmonic Distortion V = 1Vrms f = 1KHz Signal to Noise Ratio Channel Separation f = 1KHz Input Gain AUX1 1dB step 0 Parameter Min. 6 2.1 Typ. 9 2.6 0.01 106 80 15 0.08 Max. 10.2 Unit V Vrms % dB dB dB
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ELECTRICAL CHARACTERISTICS (VS = 9V; RL = 10K; Rg = 50; Tamb = 25C; all gains = 0dB; f = 1KHz. Refer to the test circuit, unless otherwise specified.)
Symbol Parameter Test Condition Min. Typ. Max. Unit
INPUT STAGE: AUX1
RI VCL SI GI MIN GI MAX Gstep Ea VDC Input Resistance Clipping Level Input Separation Minimum Input Gain Maximum Input Gain Step Resolution Set Error DC Steps Adiacent Gain Steps GIIN to GIMAX d 0.3% 24 2.1 70 -0.75 13.75 0.5 -1.25 33 2.6 80 0 15 1.0 0 0.5 2.5 0.75 16.25 1.5 1.25 10 42 K VRMS dB dB dB dB dB mV mV
SPEAKER ATTENUATORS - AUX 1
C RANGE Astep AMUTE EA VDC Control Range Step Resolution Output Mute Attenuation Attenuation Set Error DC Steps Av = 0 to -40dB Data Word = 1111XXXX Av = 0 to -40dB Adjacent Attenuation Steps 0 0.5 80 79 1 105 1.5 3 1.5 dB dB dB dB mV
AUDIO OUTPUT (Pin 4 - 5, 8 - 9, 10 - 14)
Vclip RL RO VDC Clipping Level Output Load Resistance Output Impedance DC Voltage Level d = 0.3% 2.1 2 20 3.5 30 3.8 100 4.1 2.6 Vrms K V
STAGE: AUX2
RI VCL SI GI Input Resistance Clipping Level Input Separation Gain Input Mute 24 2.1 70 -0.75 80 33 2.6 80 0 100 0.75 42 K Vrms dB dB dB
STAGE: HP FILTER
R1 R2 VCL Resistance at pin HP1 Resistance at pin HP2 Clipping Level HIGHPASS BYTE D3 = 1 d 0.3% 120 XXXX1XXX 2.1 170 1 2.6 220 K M Vrms
SOFT MUTE
AMUTE TDON TDOFF Mute Attenuation ON Delay Time OFF Current CCSM = 22nF; 0 to -20dB; I = IMAX CCSM = 22nF; 0 to -20dB; I = IMIN VCSM = 0V; I = IMAX VCSM = 0V; I = IMIN 40 0.7 10 60 110 50 1 30 2 50 160 210 dB ms ms A A
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ELECTRICAL CHARACTERISTICS (continued)
Symbol VTHSM RINT VSMH VSML Parameter Soft Mute Threshold Pullup Resistor (pin 3) (pin 3) Level High (pin 3) Level Low Soft Mute Active (note 2) 3.5 1 Test Condition Min. Typ. 2.3 100 Max. Unit V K V V
GENERAL
VCC ICC PSRR e NO S/N SC d Supply Voltage Supply Current Power Supply Rejection Ratio Output Noise Signal to Noise Ratio Channel Separation Distortion VIN =1V f = 1KHz Output Muted (B = 20 to 20kHz flat) All Gains 0dB (B = 20 to 20kHz flat) All Gains = 0dB; VO = 1Vrms 70 6 7 60 9 11 70 3.5 5 106 80 0.01 0.08 15 10.2 15 V mA dB V V dB dB %
BUS INPUTS
VIL V lN IlN VO Input Low Voltage Input High Voltage Input Current Output Voltage SDA Acknowledge VIN = 0.4V IO = 1.6mA 3 -5 5 0.4 1 V V A V
Note 1: WIN represents the MUTE programming bit pair D6, D5 for the zero crossing window threshold Note 2: Internall pullup resistor to Vs/2; "LOW" = softmute active
Figure 1: HP Filter.
56K
18.7K
9.3K
7.6K
56K
4.3K
3.5K
52.5K + 100nF HP2 100nF HP1 6.2K 3.5K 2.1K 3.8K 4.6K 9.3K 28K -
R1 = EQUIVALENT RESISTANCE AT PIN HP1 R2 = EQUIVALENT RESISTANCE AT PIN HP2 28K
D96AU439
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TDA7435
I2C BUS INTERFACE Data transmission from microprocessor to the TDA7435 and viceversa takes place thru the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be externally connected). Data Validity As shown in fig. 2, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. Start and Stop Conditions As shown in fig.3 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. A STOP conditions must be sent before each START condition. Byte Format Every byte transferred to the SDA line must conFigure 2: Data Validity on the I2CBUS tain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. Acknowledge The master (P) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 4). The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. The audioprocessor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. Transmission without Acknowledge Avoiding to detect the acknowledge of the audioprocessor, the P can use a simplier transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking and decreases the noise immunity.
Figure 3: Timing Diagram of I2CBUS
2 Figure 4: Acknowledge on the I CBUS
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TDA7435
SOFTWARE SPECIFICATION Interface Protocol The interface protocol comprises: A start condition (s) A chip address byte,(the LSB bit determines read/write transmission) A subaddress byte. A sequence of data (N-bytes + acknowledge) A stop condition (P)
CHIP ADDRESS
SUBADDRESS
DATA 1 to DATA n
MSB S 1 0 0 0 1 0
LSB
MSB X X I
LSB X A2 A1 A0 ACK
MSB DATA
LSB
ACK P
1 R/W ACK X
ACK = Acknowledge S = Start P = Stop I = Auto Increment X = Not used MAX CLOCK SPEED 500kbits/s
AUTO INCREMENT If bit I in the subaddress byte is set to "1", the autoincrement of the subaddress is enabled SUBADDRESS (receive mode)
MSB X X X I X D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 LSB D0 0 1 0 1 0 1 0 1 Mux & Gain Mute Speaker Attenuator AUX 1 L Speaker Attenuator AUX 1 R High Pass Filter FL High Pass Filter FR High Pass Filter RL High Pass Filter RR FUNCTION
TRANSMITTED DATA Send Mode
MSB X X X X X SM X LSB X
SM = Soft mute activated (HIGH active) X = Not used The transmitted data is automatically updated after each ACK. Transmission can be repeated without new chipaddress.
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DATA BYTE SPECIFICATION MUX & GAIN
MSB D7 D6 D5 D4 D3 D2 D1 LSB D0 FUNCTION
AUX 1 Input Gain
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0dB 1dB 2dB 3dB 4dB 5dB 6dB 7dB 8dB 9dB 10dB 11dB 12dB 13dB 14dB 15dB
AUX 2 Output Selection
0 0 1 1 0 1 0 1 High Pass Filter Front High Pass Filter Rear Aux 2 Input Mute
Mute
MSB D7 D6 D5 D4 D3 D2 D1 0 0 0 1 0 1 0 0 LSB D0 0 1 FUNCTION Soft mute - SLOW SLOPE Soft mute - FAST SLOPE Soft mute ON Soft mute OFF AUX 1 Input Mute Enabled AUX 1 Input Mute Disabled
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TDA7435
Speaker
MSB D7 D6 D5 D4 D3 D2 D1 LSB D0 AUX 1 L, R
-1dB STEPS
0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0dB -1dB -2dB -3dB -4dB -5dB -6dB -7dB
-8dB STEPS
0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 0 1 1 MUTE 0 1 0 1 0 1 0 1 0 1 0dB -8dB -16dB -24dB -32dB -40dB -48dB -56dB -64dB -72dB
HIGH PASS FILTERS
MSB D7 D6 D5 D4 D3 D2 D1 LSB D0 FL, FR, RL, RR
2nd order HP Filter Mode (C1 = C2 = 100nF)
0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 fc = 40Hz fc = 60Hz fc = 80Hz fc = 100Hz fc = 120Hz fc = 150Hz fc = 180Hz fc = 220Hz
First order HP Flat Mode
1 fc = 9Hz
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TDA7435
SO28 PACKAGE MECHANICAL DATA
DIM. MIN. A a1 b b1 C c1 D E e e3 F L S 7.4 0.4 17.7 10 1.27 16.51 7.6 1.27 8 (max.) 0.291 0.016 18.1 10.65 0.1 0.35 0.23 0.5 45 (typ.) 0.697 0.394 0.050 0.65 0.299 0.050 0.713 0.419 mm TYP. MAX. 2.65 0.3 0.49 0.32 0.004 0.014 0.009 0.020 MIN. inch TYP. MAX. 0.104 0.012 0.019 0.013
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Purchase of I2C Components of SGS-THOMSON Microlectronics, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips.
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as criticalcomponents in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1996 SGS-THOMSON Microelectronics - Printed in Italy - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
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